1. Field of the Invention
This invention relates to real-time multiresolution signal processing apparatus, which is useful in performing hierarchial pyramid signal processing techniques for analyzing the frequency spectrum of an information component (having one or more dimensions) of a given temporal sampled signal having a highest frequency of interest no greater than f.sub.0, and/or for synthesizing such a temporal signal from the analyzed frequency spectrum thereof.
2. Description of the Prior Art
Reference is made to co-pending U.S. patent application Ser. No. 596,817, entitled "Real-Time Hierarchical Pyramid Signal Processing Apparatus," filed Apr. 4, 1984, by Curtis R. Carlson, et al., issued June 16, 1987, as U.S. Pat. No. 4,674,125 and assigned to the same assignee as the present invention. This co-pending Carlson, et al. application discloses apparatus employing pipeline architecture for implementing a hierarchical pyramid capable of either analyzing in delayed real time the frequency spectrum of an information component (having one or more dimensions) of a given temporal signal, or synthesizing in delayed real time such a temporal signal from the analyzed frequency spectrum thereof. Such pipeline architecture is particularly suitable for image processing the two dimensional spatial frequencies of television images defined by a temporal video signal.
In accordance with each of different species of the invention disclosed in the aforesaid Carlson, et al. application, the real-time hierarchical pyramid signal processing apparatus operates, alternatively, as a Burt Pyramid analyzer, a Burt Pyramid synthesizer, or a filter-subtract-decimate (FSD) pyramid analyzer. The FSD species of the Carlson, et al. generic invention is not specifically the invention of Carlson, et al., but is the invention of Charles Hammond Anderson. For this reason, the aforesaid Carlson, et al. application specifically disclaims the FSD pyramid analyzer species of the Carlson, et al. generic invention.
Reference is further made to co-pending U.S. patent application Ser. No. 774,984, entitled "A Filter-Subtract-Decimate Hierarchical Pyramid Signal Analyzing And Synthesizing Technique," filed Sept. 11, 1985, by Charles H. Anderson, and assigned to the same assignee as the present invention. This co-pending Anderson application discloses and specifically claims the FSD pyramid analyzer species of the generic invention disclosed in the aforesaid co-pending Carlson, et al. application.
The implementation of the real-time pyramid analyzer disclosed in the aforesaid co-pending Carlson, et al. application, is comprised of N separate cascaded stages, where N is a given plural integer. Similarly, the implmentation of the real-time pyramid synthesizer disclosed in the aforesaid co-pending Carlson, et al. application is comprised of N separate cascaded stages. Each of these stages employs a relatively large amount of digital hardware, particularly when the information component of the temporal signal is defined by more than one dimension (e.g., a video signal comprised of a serial stream of 8-bit pixel samples that define successive frame of a scanned two-dimensional television image). Thus, the total amount of hardware employed by the Carlson, et al. implementation tends to be quite large.
Reference is further made to co-pending U.S. patent application Ser. No. 768,809, entitled "Multiplexed Real-Time Pyramid Signal Processing System" filed Aug. 23, 1985, by Roger F. Bessler, et al., and assigned to the same assignee as the present invention. This co-pending Bessler, et al. application makes use of time multiplexing to greatly reduce the amount of hardware required to implement a real time pyramid signal processing system.
A first feature that both the real-time pyramid systems disclosed respectively in the aforesaid co-pending Carlson, et al. application and Bessler, et al. application have in common is that they are completely time synchronous. The expression "time synchronous," as used herein, means that in such a pyramid analyzer, there is a predetermined fixed set of respective delays between the occurence of each pixel sample of the input serial stream of pixel samples and the occurrence anywhere either in any of the analyzer stages or at the output of any of the analyzer stages of those respective pixel samples that correspond to that input pixel sample. Such complete time synchronous relationship is also true for the occurrence of all corresponding pixel samples of all the stages of the pyramid synthesizer. This means that all corresponding samples must move through the entire pyramid perfectly (i.e., without any timing errors) for proper operation, despite the long delay which occurs between the occurrence of an input pixel sample to such a pyramid analyzer and the occurence of its corresponding pixel sample of at least one of the analyzed subspectra outputs. This delay can amount to many tens of thousands of pixel sample periods. Further, because of the severe timing constraints on such a completely time-synchronous pyramid system, it is limited, for the most part, to a single predetermined mode of operation, so that a time-synchronous pyramid system cannot be programmed to any appreciable extent.